Electrostatic discharge (ESD) is the movement of static electricity from a nonconductive surface, which could cause damage to semiconductors and other circuit components in integrated circuits. A person walking on a carpet, for instance, can carry an electrostatic charge of up to several thousands of volts under high humidity conditions and over 10000 volts under low humidity conditions. ESD may be imparted to an integrated circuit within an IC package when the integrated circuit or the IC package is contacted by an electrostatic charge source that may be encountered during assembly or afterwards when the device is in the field. When “zapped”, i.e., subjected to electrostatic discharge, the instantaneous power level of the ESD could cause severe damage to the integrated circuits.
An IC package typically includes a metal lead frame or other package substrate coupled to a semiconductor chip. The semiconductor chip includes the integrated circuit which has several active bond pads that couple the integrated circuit to outside components. The metal lead frame or other package substrate includes a plurality of pins or other contacts that are coupled to respective bond pads of the integrated circuit formed on the semiconductor chip. The coupling may be achieved by wire bonding to a metal lead frame, for example, or it may be achieved by flip-chip packaging which involves directly joining the contact areas of the package substrate to corresponding bond pads of the semiconductor chip using solder bump. In a typical IC package, the metal lead frame includes at least one pin that is not coupled to a corresponding bond pad. Such pins are referred to as non-wired or non-coupled pins.
In the prior art arrangement shown in FIG. 1, IC package 115 includes semiconductor chip 101 coupled to lead frame 103. Lead frame 103 includes a plurality of pins including coupled pins 105 and non-coupled pins 107. Coupled pins 105 are coupled by means of wire bonds 111 to corresponding bond pads 113 that are coupled to, and form part of, the integrated circuit formed on semiconductor chip 101. In contrast, non-coupled pins 107 of lead frame 103 are not coupled to semiconductor chip 101 in conventional designs.
During handling, installation, testing and use in the field, the coupled pins and the non-coupled pins are equally likely to be subjected to electrostatic discharge, i.e., zapped. When one of the non-coupled pins is subjected to ESD, it may induce ESD failure on the adjacent, coupled pin which was not zapped. More particularly, when the non-wired pin becomes subjected to ESD discharge, it may damage active circuit components of the integrated circuit by coupling the electrostatic discharge through the adjacent, coupled pin, to the bond pad and therefore the integrated circuit.
ESD damage due to an adjacent pin being zapped is discussed in detail in a paper entitled “New Failure Mechanism Due to No-connect Pin ESD Stressing”, by Matsumoto of Japan in 1994 EOS/ESD Symposium, pp. 90-95. The paper reveals the fact that, when a human body model (HBM) ESD pulse is repeatedly applied to a no-contact pin on an IC package, any of the two neighboring pins, if wired to the internal circuit, would become vulnerable to ESD damage. This is because the electrostatic charge will accumulate in the resin around the no-contact pin resulting in a large potential difference between the no-contact pin and its neighboring pins, which would significantly reduce the ESD resistance capability of the neighboring pins.
It would therefore be desirable to reduce the probability of ESD damaging a device through a coupled pin due to a non-coupled pin being subjected to electrostatic discharge.